1. Field of the Invention
The present invention relates to an arithmetic operation system and more particularly, to an arithmetic operation system that operates arithmetically a first operand having a point and a second operand having no point without using any dedicated floating-point arithmetic operating subsystem such as a floating-point arithmetic operating processor and a floating-point arithmetic operating digital signal processor (DSP).
2. Description of the Prior Art
When an arithmetic operation giving an output y by multiplying a variable x having no point by a gain k having a point (i.e., y=k.multidot.x) is performed in electronic control applications, floating-point arithmetic operation is essentially needed.
In conventional microcomputer application systems of this sort, a dedicated floating-point arithmetic operating DSP is additionally provided together with a microcomputer to provide a floating-point arithmetic operation. Alternately, a high-performance microcomputer incorporating a floating-point arithmetic operating function is used. This is because a typical microcomputer or DSP is capable of integer arithmetic operation (i.e., fixed-point arithmetic operation) only.
However, the conventional microcomputer application systems equipped with the dedicated floating-point arithmetic operating DSP has a problem that the dedicated DSP raises the fabrication cost of the microcomputer application systems. The conventional microcomputer application systems equipped with the high-performance microcomputer incorporating the floating-point arithmetic function has a problem that a dedicated floating-point arithmetic operation unit needs to be provided for realizing the floating-point arithmetic function, resulting in a raised fabrication cost of the microcomputer application systems.
A floating-point multiplier applicable to the above dedicated floating-point arithmetic operation unit is disclosed in the Japanese Non-Examined Patent Publication No. 2-183828 published in 1990.
However, the conventional floating-point multiplier disclosed in the Japanese Non-Examined Patent Publication No. 2-183828 has a problem that this multiplier has a complex configuration. This is because, unlike a fixed-point multiplier, this multiplier requires various dedicated circuits such as a rounding circuit for rounding the significands of numbers to be multiplied, shifters for arithmetically shifting the significands and exponents, adders for the exponents, carry detectors, and multiplexers.
To solve the above problems, and improvement was reported in an article entitled "whole power electronics" of the book entitled "OHM", Vol. 9, p.95, 1993, published by Ohm publishing Co. Ltd.. In this improvement, a floating-point arithmetic operation is performed with the use of a typical microcomputer capable of an integer (i.e., fixed-point) arithmetic operation and a dedicated software produced therefor. This software has the following steps as shown in FIG. 1.
Here, as shown in FIG. 2, it is supposed that the gain K is m bits wide and has a fraction of n bits in width, where n&lt;m. Therefore, the most significant bit (MSB) of the gain K is bit (m-1) and the least significant bit (LSB) thereof is bit 0. An actual binary point P is located between bit n and bit (n-1).
In the step S1 shown in FIG. 1, the gain K is shifted left by n bits (i.e., the gain K is multiplied by 2.sub.ten.sup.n) to convert it to an integer coefficient k. The coefficient k has an assumed binary point P' located between bit (n-1) and bit n, as shown in FIG. 2.
In the step S2, the integer coefficient k is multiplied by the fraction variable x, producing a product Y (i.e., Y=k.multidot.x).
In the step S3, it is judged whether the fraction of the product Y is less than 0.1 in binary (i.e., 0.1.sub.two) or not. The number 0.1 in binary is equal to a number 0.5 in decimal (i.e., 0.5.sub.ten). This judgment is carried out to round off the product Y at bit (n-1), thereby minimizing the rounding error of the product y.
When the assumed fraction of the product Y, which is located during bit (n-1) and bit 0, is not less than 0.1.sub.two or 0.5.sub.ten, a variable T is set as 1 in binary (i.e., 1.sub.two) in the step S4. This step S4 is performed for the purpose of rounding off the product Y to "1.sub.two " as bit n.
Then, the variable T of 1.sub.two is shifted left by n bits in the step S6. The left-shifted variable T is added to the product Y in the step S7.
Finally, the product Y is shifted right by n bits (i.e., the product Y is divided by 2.sub.ten.sup.n), thereby producing the rounded product y of the gain K and the variable x in the step S8. The actual point P of the product y is located at the right side of bit 0 due to the above rounding off. In other words, the product y has an integer value.
On the other hand, when the assumed fraction of the product Y is less than 0.1.sub.two or 0.5.sub.ten, the variable T is set as 0.sub.two in the step S5.
Then, the variable T of 0.sub.two is shifted left by n bits in the step S6. The left-shifted variable T is added to the product Y in the step S7. Because the variable T has a value of 0.sub.two, no change occurs in the value of the product Y.
Finally, the product X is shifted right by n bits, thereby producing the rounded product y of the gain K and the variable x in the step S8.
In the microcomputer application systems, the arithmetic operation accuracy is dependent upon the way how to operate arithmetically the fraction of a data value. Therefore, the arithmetic operation method for the fraction of a data value is very important in view of operation accuracy.
For example, in feedback control systems such as position control systems using electric motors, arithmetic operation of the integrated data values including fraction numbers is essentially required. In this case, the arithmetic operation method for the fraction of a data value largely affects the control accuracy of the feedback control systems.
With the conventional floating-point arithmetic operation with the use of a dedicated software shown in FIG. 1, a wanted operation accuracy may be realized. However, in this case, the floating-point arithmetic operation is performed by executing the software by a central processing unit (CPU) of a microcomputer in a microcomputer application system. As a result, there is a problem that it takes a long time to complete the arithmetic operation. This means that the above conventional floating-point arithmetic operation using the software is unable to be applied to microcomputer application systems necessitating high-speed control actions.
On the other hand, the occurrence rate of the processes necessitating the floating-point arithmetic operation is not high within the overall processes of the microcomputer application systems. Therefore, even if a dedicated floating-point arithmetic operating DSP or a dedicated floating-point arithmetic operation unit is additionally introduced, the high-cost dedicated DSP or unit thus introduced is not effectively utilized.